MIPS Program Sequence : 662388 – My Assignment Help : Samples & Case Study Review Sample

Question:

You will be given an input file containing a sequence of 32 bit instruction words. Assume that the first instruction is at memory address 96. The final instruction in an instruction sequence is ALWAYS a “BREAK” instruction. Following the break instruction is a sequence of 32 bit 2’s compliment signed integers for the program data. These continue until the end of file.

Your simulator/dissassembler must support the following MIPS instructions:

J, JR, BEQ, BLTZ

ADD, ADDI, SUB

SW, LW

SLL, SRL

MUL,

AND, OR,

MOVZ

NOP

BEQ and BLTZ will use the following implementation:

PC + 4 + offset in the intermediate field. There will be no shifting as is described in the MIPS documentation.

J will jump to the instruction enumerated in the immediate field left shifted by 2 i.e. 28 in the immediate field means instruction 112.

JR will jump directly to the instruction located in the register specified in the instruction. i.e. if $r4 has 132 in it, JR R4 will jump to instruction 132

Your program must accept command line arguments for execution. The following arguments must be supported:

$ python team#_project1.py -i test1_bin.txt -o team#_out

Your program will produce 2 output files. One named team#_out_sim.txt, which contains the simulation output, and one named team#_out_dis.txt, which contains the disassembled program code for the input MIPS machine code.

Your program will be graded both with the sample input and output provided to you, and with input and output that is not provided to you. It is recommended you construct your own input programs for testing.

Output: The dissembled output file should contain one line per word in the input file. It should be separated into 4 columns, each separated by tab character. The columns contain the following information:

The binary representation of the instruction word. If the word is an instruction (as opposed to memory data after the BREAK instruction), the instruction should be split into seven groups of digits: the valid bit, the opcode bits, four groups of 5 bits, and a final group of 6 bits.

The address of the memory location (in decimal)
If it is an instruction, print the operation, followed by a tab character, then print each argument separated by a comma and a space ( “, “).

The simulation file have the following format:

20 equal signs and a newline
cycle: [cycle number] [tab] [instruction address] [tab] [instruction string (same as step 3 above)]
[blank line]
registers:
r00: [tab] [integer value of R00][tab] [integer value of R01][tab] …[integer value of R07]
r08: [tab] [integer value of R08][tab] [integer value of R09][tab] …[integer value of R15]
r16: [tab] [integer value of R16][tab] [integer value of R17][tab] …[integer value of R23]

r24: [tab] [integer value of R24][tab] [integer value of R25][tab] …[integer value of R31]

[blank line]

data:

[data address]: [tab] [show 8 data words, with tabs in between]

…[continue until last data word]

Instructions and arguments should be in capital letters. All integer values should be in decimal. Immediate values should be preceded by a # sign. Be careful and consider which instructions take signed values and which take unsigned values. Be sure to use the correct format depending on the context.

You output will be graded with the DIFF command. Test your output against the provided sample outputs! Any differences reported by the DIFF command are assumed to be incorrect output! That is why the formatting is so prescribed!!!!!!!!! If you don’t follow it you will get hammered on the grading. 🙁

What to turn in: Your source file. A README.txt file indicating how to run your program on LINUX!! Also, it should contain the names and txstate netIDs of your group members. You can develop on Windows, but your program will be graded on Linux on my mac powerbook. The executable must be named “team#_project1.py”. I also want a test input file you ran – preferably the one I gave you – and the outputs for the test file. This is case your code will not run MY final test file.

You should turn in one folder with all the files in it with the folder name “team#_project1”. I want to be able to drop in my testing program and run your code.

Coding Suggestions: I suggest that you break your code into two independent sections and put your disassembly output into series of lists for input to the simulator. This will be absolutely needed for project two so do it now.

Think about all data structures before you start. If you want me to review your plan, come by my office hours.

The basic idea for the disassembler is a for loop to march through all of the instructions.

The basic idea for the simulator is a do while loop since there is branching and looping. They are do very different situations and cannot readily be combined. DON’T TRY!

We will talk about unit testing. I cannot emphasize enough about developing your own set of tests since the ones I give you are not complete!!

Answer:

import sys

checkD = []

op = []

rs = []

rt = []

rd = []

shamt = []

func = []

imm = []

addr = []

ins = []

inst2 = []

regReady = []

mem = []

PC = 96

cache = [[0, 0, 0, 0, 0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0] ]

##[tag, valid, dirty, i1, i2]

LRU = [4]

preIssue = []

preMem = []

preAlu = []

postMem = []

postAlu = []

instruc= []

justChecked = []

keepFetching = True

fetch = True

inCache = False

pcounter = 0

inFile = open(“t1test_bin.txt”, “r”) # inputFileName

inst = inFile.readlines()

inFile.close()

outFile = open(“t5” + “_dis.txt”, “w”) # outputFileName

# symFile = open(outputFileName + “_sym.txt”, “w”)

iNum = 0

#——————————————-DISASSEMBLER———————————————

def getR(ns):

return str(int(ns, 2))

def getImm(ns):

tem = int(ns, 2)

if (tem > 65530):

tem = tem – (1 << 16)

return str(tem)

def getR2(ns):

tem = int(ns, 2)

if (tem > 65530):

tem = tem – (1 << 16)

r = tem * 4 ## May be not * 4 for new specs???

return str(r)

def getR3(ns):

tem = int(ns, 2)

if (tem > 67108860):

tem = tem – (1 << 16)

r = tem * 4

return str(r)

def update_register(l, iNum):

#print ” l ” + str(l)

#print “iNum ” + str(iNum)

if (op[l] == “00000”):

# print(“I m coo”)

# print(“func is ” + func[l])

# print(type(func[l]))

if (func[l] == “100000”):

# ins[l] = “ADD”+”\t”+”R”+getR(rd[l])+”, R”+getR(rs[l])+”, R”+getR(rt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rs[l]))

t3 = int(getR(rt[l]))

# print(“I m coo2”)

elif (func[l] == “100100”):

# ins[l] = “AND”+”\t”+”R”+getR(rd[l])+”, R”+getR(rs[l])+”, R”+getR(rt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rs[l]))

t3 = int(getR(rt[l]))

elif (func[l] == “001000”):

# ins[l] = “JR”+”\t”+”R”+getR(rs[l])

t1 = int(getR(rs[l]))

####################################################

#print ” l, JR ” + str(l)

#print ” register[t1]-96/4 ” + str((int(register[t1]) – 96) / 4)

#print type(register[t1])

l = ((int(register[t1]) – 96) / 4)

l = l – 1

#print ” after /4 ” + str(l)

###################################################

elif (func[l] == “000000”):

if (not (rt[l] == “00000” and rd[l] == “00000” and shamt[l] == “00000”)):

# ins[l] = “NOP ”

# pass

# else:

# ins[l]= “SLL”+”\t”+”R”+getR(rd[l])+”, R”+getR(rt[l])+”, #”+getR(shamt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rt[l]))

t3 = int(getR(shamt[l]))

elif (func[l] == “100101”):

# ins[l] = “OR”+”\t”+”R”+getR(rd[l])+”, R”+getR(rs[l])+”, R”+getR(rt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rs[l]))

t3 = int(getR(rt[l]))

elif (func[l] == “000010”):

# ins[l] = “SRL”+”\t”+”R”+getR(rd[l])+”, R”+getR(rt[l])+”, #”+getR(shamt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rt[l]))

t3 = int(getR(shamt[l]))

elif (func[l] == “100010”):

# ins[l] = “SUB”+”\t”+”R”+getR(rd[l])+”, R”+getR(rs[l])+”, R”+getR(rt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rs[l]))

t3 = int(getR(rt[l]))

elif (func[l] == “001010”):

# ins[l] = “MOVZ”+”\t”+”R”+getR(rd[l])+”, R”+getR(rs[l])+”, R”+getR(rt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rs[l]))

t3 = int(getR(rt[l]))

if (int(register[t3]) == 0):

# elif (func[l] == “001101\n”):

# ins[l] = “BREAK ”

elif (op[l] == “11100”):

if (func[l] == “000010”):

# ins[l]= “MUL”+ “\t”+”R”+getR(rd[l])+”, R”+getR(rs[l])+”, R”+getR(rt[l])

t1 = int(getR(rd[l]))

t2 = int(getR(rs[l]))

t3 = int(getR(rt[l]))

elif (op[l] == “00011”):

# ins[l] = “LW”+ “\t”+”R”+getR(rt[l])+”, “+getR(imm[l])+”(“+”R”+getR(rs[l])+”)”

t1 = int(getR(rt[l]))

t2 = int(getR(imm[l]))

t3 = int(getR(rs[l]))

mloc = ((t2 + int(register[t3])) – int(addr[iNum – 1])) / 4

# print(mloc)

# print(t1)

# print(t2)

# print(t3)

# print(mloc)

elif (op[l] == “00001”):

# ins[l]=”BLTZ”+ “\t”+”R”+getR(rs[l])+”, #”+getR2(imm[l])

t1 = int(register[int(getR(rs[l]))])

t2 = int(getR2(imm[l])) / 4

if (t1 < 0):

l += t2

# print(t1)

# print(t2)

# print(l)

elif (op[l] == “00100”):

# ins[l] = “BEQ”+ “\t”” + “R” + getR(rs[l]) + “R”+getR(rt[l])+ “, #” + getR2(imm[l])

t1 = int(register[int(getR(rs[l]))])

t2 = int(getR2(imm[l])) / 4

if (t1 == 0):

l += t2

elif (op[l] == “01011”):

# ins[l] = “SW”+”\t”+”R”+getR(rt[l])+”, “+getR(imm[l])+”(“+”R”+getR(rs[l])+”)”

t1 = int(getR(rt[l]))

t2 = int(getR(imm[l]))

t3 = int(getR(rs[l]))

mloc = ((t2 + int(register[t3])) – int(addr[iNum – 1])) / 4

ins[iNum – 1 + mloc] = register[t1]

elif (op[l] == “01000”):

# ins[l] = “ADDI”+”\t”+”R”+getR(rt[l])+”, R”+getR(rs[l])+”, #”+getImm(imm[l])

t1 = int(getR(rt[l]))

t2 = int(getR(rs[l]))

t3 = int(getImm(imm[l]))

elif (op[l] == “00010”):

# ins[l] = “J”+”\t” + “#”+getR3(imm[l])

t1 = int(getR3(imm[l]))

t2 = t1 – 96

l = (t2 / 4) – 1

# print(“here”+str(l))

# print ” post l ” + str(l)

# print “post iNum ” + str(iNum)

return l

def reg(l):

rs[l] = inst[l][6:11]

rt[l] = inst[l][11:16]

rd[l] = inst[l][16:21]

shamt[l] = inst[l][21:26]

func[l] = str(inst[l][26:]).rstrip(‘\n’)

getReg(l, iNum)

def im(l):

rs[l] = inst[l][6:11]

rt[l] = inst[l][11:16]

imm[l] = inst[l][16:]

getReg(l, iNum)

def j(l):

imm[l] = inst[l][6:]

getReg(l, iNum)

def printThis(l):

thisStr = inst[l][0:1] + ” ” + inst[l][1:6] + ” ” + inst[l][6:11] + ” ” + inst[l][11:16] + ” ” + inst[l][

16:21] + ” ” + \

inst[l][21:26] + ” ” + inst[l][26:].rstrip(‘\n’) + “\t” + addr[l] + “\t” + ins[l] + “\n”

outFile.write(thisStr)

def printThat(l):

thatStr = inst[l].rstrip(‘\n’) + “\t” + addr[l] + “\t” + ins[l] + “\n”

outFile.write(thatStr)

def getReg(l, inum):

if (op[l] == “00000”):

# print(“I m coo”)

# print(“func is ” + func[l])

# print(type(func[l]))

if (func[l] == “100000”):

ins[l] = “ADD” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rs[l]) + “, R” + getR(rt[l])

elif (func[l] == “100100”):

ins[l] = “AND” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rs[l]) + “, R” + getR(rt[l])

elif (func[l] == “001000”):

ins[l] = “JR” + “\t” + “R” + getR(rs[l])

elif (func[l] == “000000”):

if (rt[l] == “00000” and rd[l] == “00000” and shamt[l] == “00000”):

ins[l] = “NOP ”

else:

ins[l] = “SLL” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rt[l]) + “, #” + getR(shamt[l])

elif (func[l] == “100101”):

ins[l] = “OR” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rs[l]) + “, R” + getR(rt[l])

elif (func[l] == “000010”):

ins[l] = “SRL” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rt[l]) + “, #” + getR(shamt[l])

elif (func[l] == “100010”):

ins[l] = “SUB” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rs[l]) + “, R” + getR(rt[l])

elif (func[l] == “001010”):

ins[l] = “MOVZ” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rs[l]) + “, R” + getR(rt[l])

elif (func[l] == “001101”):

ins[l] = “BREAK ”

inum = l

elif (op[l] == “11100”):

if (func[l] == “000010”):

ins[l] = “MUL” + “\t” + “R” + getR(rd[l]) + “, R” + getR(rs[l]) + “, R” + getR(rt[l])

elif (op[l] == “00011”):

ins[l] = “LW” + “\t” + “R” + getR(rt[l]) + “, ” + getR(imm[l]) + “(” + “R” + getR(rs[l]) + “)”

elif (op[l] == “00001”):

ins[l] = “BLTZ” + “\t” + “R” + getR(rs[l]) + “, #” + getR2(imm[l])

elif (op[l] == “00100”):

ins[l] = “BEQ” + “\t” + “R” + getR(rs[l]) + “, ” + “R” + getR(rt[l]) + “, #” + getR2(imm[l])

elif (op[l] == “01011”):

ins[l] = “SW” + “\t” + “R” + getR(rt[l]) + “, ” + getR(imm[l]) + “(” + “R” + getR(rs[l]) + “)”

elif (op[l] == “01000”):

ins[l] = “ADDI” + “\t” + “R” + getR(rt[l]) + “, R” + getR(rs[l]) + “, #” + getImm(imm[l])

elif (op[l] == “00010”):

ins[l] = “J” + “\t” + “#” + getR3(imm[l])

#———————————————PIPELINE———————————————

def dec_to_bin(x):

return (bin(int(x))[2:])

def findTag(ind):

offset = dec_to_bin(addr[ind])

offset = offset[0:-5]

thisTag = int(offset, 2)

return thisTag

def findSet(ind):

# if(ind % 2 != 0):

# ind = ind- 1

offset = dec_to_bin(addr[ind])

offset = offset[-5:-3]

thisSet = int(offset, 2)

return thisSet

def checkCache(ind):

if (ind % 2 != 0 and ind!=0):

ind = ind – 1

#print(ind)

thisSet = findSet(ind)

checkVar = -1

if(thisSet==0):

if(cache[0][0]== ind and cache[0][1] == 1 ):

LRU[0] = 0

checkVar = 0

elif(cache[1][0]== ind or cache[1][1]== 1):

LRU[0] = 1

checkVar = 1

elif(thisSet==1):

if(cache[2][0]== ind and cache[2][1] == 1):

LRU[1] = 2

checkVar = 2

elif(cache[3][0]== ind or cache[3][1]== 1):

LRU[1] = 3

checkVar = 3

elif(thisSet==2):

if(cache[4][0]== ind and cache[4][1] == 1):

LRU[2] = 4

checkVar = 4

elif(cache[5][0]== ind or cache[5][1]== 1):

LRU[2] = 5

checkVar = 5

elif(thisSet==3):

if(cache[6][0]== ind and cache[6][1] == 1):

LRU[3] = 6

checkVar = 6

elif(cache[7][0]== ind or cache[7][1]== 1):

LRU[3] = 7

checkVar = 7

return checkVar

def storeLRU(storeInd):

if(storeInd >= iNum):

ins[cache[storeInd][0]] = cache[storeInd][3]

ins[(cache[storeInd][0])+1] = cache[storeInd][4]

def updateCache(ind):

if (ind % 2 != 0):

ind = ind – 1

thisSet = findSet(ind)

#if (thisSet == 0):

if(cache[LRU[thisSet]][2] == 1):

storeLRU(LRU[thisSet])

cache[LRU[thisSet]][0]=ind

cache[LRU[thisSet]][1]= 1

cache[LRU[thisSet]][2]= 0

cache[LRU[thisSet]][3]= ins[ind]

cache[LRU[thisSet]][4]= ins[ind+1]

def infetch(ind):

global pcounter

print(‘infetch’)

print(ind)

print(pcounter)

if (ins[instruc[ind]][0:1] == “Invalid Instruction”):

print(inst[instruc[ind]])

pcounter += 1

elif (func[instruc[ind]] == “001000”): # JR

fetch = False

if (ind == 0):

del instruc[1]

t1 = int(getR(rs[instruc[ind]]))

if (regReady[t1]):

pcounter = ((int(register[t1]) – 96) / 4)

pcounter = pcounter

del instruc[ind]

# ind -= 1

# chLen -=1

fetch = True

elif (op[instruc[ind]] == “00001”): # BLTZ

fetch = False

if (ind == 0):

del instruc[1]

t1 = int(getR(rs[instruc[ind]]))

if (regReady[t1]):

t2 = int(register[t1])

t3 = int(getR2(imm[instruc[ind]])) / 4 # ARE WE NOT DIVIDING BY 4 FOR THIS?

if (t2 < 0):

pcounter += t3

del instruc[ind]

fetch = True

elif (op[instruc[ind]] == “00100”): # BEQ

fetch = False

if (ind == 0):

del instruc[1]

t1 = int(getR(rs[instruc[ind]]))

if (regReady[t1]):

t2 = int(register[t1])

t3 = int(getR2(imm[instruc[ind]])) / 4 # ARE WE NOT DIVIDING BY 4 FOR THIS?

if (t2 == 0):

pcounter += t3

del instruc[ind]

fetch = True

elif (op[instruc[ind]] == “00010”): # J

t1 = int(getR3(imm[instruc[ind]]))

t2 = t1 – 96

pcounter = (t2 / 4) # – 1 Might not need the -1

del instruc[ind]

else:

if (4 – len(preIssue) >= 1):

preIssue.append(instruc[ind])

del instruc[ind]

pcounter += 1

def iFetch():

global fetch

print(“iFetch”)

print(pcounter)

if(keepFetching and fetch):

checkVar = checkCache(pcounter)

if(checkVar >= 0):

if(4-len(preIssue)>1):

#if (inCache):

if (len(instruc)==0):

instruc.append(cache[checkVar][0]) #can just append pcounter

instruc.append(cache[checkVar][0]+1)

print(“i0: ” + str(instruc[0]))

print(“i1: ” + str(instruc[1]))

#UPDATE pcounter (there at bottom being done)

elif(4-len(preIssue)==1):

if(len(instruc)<=1):

instruc.append(pcounter) #If space for one can second be fetched???

else:

for i in range (len(justChecked)):

if(justChecked[i]==pcounter):

updateCache(pcounter)

del justChecked[i]

iFetch()

else:

justChecked.append(pcounter)

# if cache[0]>1000 and cache[1]>1000 updateChache return

chLen = len(instruc)

#print(“index: “+str(instruc[0]))

if(len(instruc)>0):

if(func[instruc[0]]==”001101″): #BREAK

keepFetching == False

if(len(instruc)>1):

del instruc[1]

elif(chLen>1):

if(func[instruc[1]]==”001101”):

keepFetching==False

if(len(instruc)==1):

infetch(0)

elif(len(instruc)==2):

infetch(0)

def issue():

if(len(preIssue)>0):

#LW, SW

l = -1

for z in range(len(preIssue)):

l=l+1

if(len(preIssue)>0):

if(op[preIssue[0]] == “00011” or op[preIssue[0]]==”01011″):

if(regReady[int(getR(rt[preIssue[0]]))]==True and regReady[int(getR(rs[preIssue[0]]))]==True):

if(len(preMem)<=1):

preMem.append(preIssue[0])

regReady[int(getR(rt[preIssue[0]]))] == False

#regReady[rs[preIssue[0]]] == False

del preIssue[0]

l=l-1

continue

# else:

#ADD, AND, MOVZ, OR, SUB, SRL

if (len(preAlu) <= 1):

if(op[preIssue[l]] == “00000”):

if(func[preIssue[l]]==”100000″ or func[preIssue[l]]==”100100″ or func[preIssue[l]]==”100101″ or func[preIssue[l]]==’100010′ or func[preIssue[l]] == “001010” or func[preIssue[l]] == “000010”):

if(regReady[int(getR(rd[preIssue[l]]))]==True and regReady[int(getR(rs[preIssue[l]]))]==True and regReady[int(getR(rt[preIssue[l]]))]==True ):

# if (len(preAlu) <= 1):

preAlu.append(preIssue[l])

#regReady[rt[preIssue[l]]] == False

#regReady[rs[preIssue[l]]] == False

regReady[int(getR(rd[preIssue[l]]))] == False

del preIssue[l]

l = l – 1

continue

#SLL

elif(func[l] == “000000” and (not(rt[l] == “00000” and rd[l] == “00000” and shamt[l] == “00000”))):

if(regReady[int(getR(rd[preIssue[l]]))]==True and regReady[int(getR(rt[preIssue[l]]))]==True):

preAlu.append(preIssue[l])

regReady[int(getR(rd[preIssue[l]]))] == False

del preIssue[l]

l = l – 1

continue

#MUL

elif(op[preIssue[l]]==”11100″ and func[preIssue[l]]==”000010″):

if(regReady[int(getR(rd[preIssue[l]]))] == True and regReady[int(getR(rs[preIssue[l]]))] == True and regReady[int(getR(rt[preIssue[l]]))] == True):

#if (len(preAlu) <= 1):

preAlu.append(preIssue[l])

# regReady[rt[preIssue[l]]] == False

# regReady[rs[preIssue[l]]] == False

regReady[int(getR(rd[preIssue[l]]))] = False

del preIssue[l]

l = l – 1

continue

#ADDI

elif (op[preIssue[l]] == “01000”):

if(regReady[int(getR(rt[preIssue[l]]))]==True and regReady[int(getR(rs[preIssue[l]]))]==True):

preAlu.append(preIssue[l])

regReady[int(getR(rt[preIssue[l]]))]==False

del preIssue[l]

l = l – 1

continue

def ALU():

if(len(preAlu)>0):

postAlu.append(preAlu[0])

#print(“Pre”)

#print (preAlu[0])

del preAlu[0]

def MEM():

if(len(postMem)>0):

if(op[preMem[0]] == “00011”):

t1 = int(getR(rt[preMem[0]]))

t2 = int(getR(imm[preMem[0]]))

t3 = int(getR(rs[preMem[0]]))

mloc = ((t2 + int(register[t3])) – int(addr[iNum – 1])) / 4

checkVar = checkCache(mloc)

if(checkVar >= 0):

postMem.append(preMem[0])

del preMem[0]

else:

for i in range (len(justChecked)):

if (justChecked[i] == mloc):

updateCache(mloc)

del justChecked[mloc]

else:

justChecked.append(mloc)

elif(op[preMem[0]] == “01011”):

t1 = int(getR(rt[l]))

t2 = int(getR(imm[l]))

t3 = int(getR(rs[l]))

mloc = ((t2 + int(register[t3])) – int(addr[iNum – 1])) / 4

checkVar = checkCache(mloc)

if (checkVar >= 0):

if(cache[checkVar][0]==mloc):

cache[checkVar][3] = register[t1]

cache[checkVar][2] = 1

del preMem[0]

elif(cache[checkVar][0]==mloc-1):

cache[checkVar][4] = register[t1]

cache[checkVar][2] = 1

else:

for i in range (len(justChecked)):

if (justChecked[i] == mloc):

updateCache(mloc)

del justChecked[mloc]

else:

justChecked.append(mloc)

def WB():

if(len(postAlu)>0):

l = postAlu[0]

update_register(l, iNum)

print(“Here”)

print(postAlu[0])

print((rt[postAlu[0]]))

regReady[int(getR(rs[postAlu[0]]))]=True

regReady[int(getR(rt[postAlu[0]]))]=True

del postAlu[0]

if (len(postMem) > 0):

l = postMem[0]

update_register(l, iNum)

regReady[int(getR(rt[postMem[0]]))] = True

del postMem[0]

def printPipeline(cycleCount):

print(“——————–\n”)

print(“Cycle: ” + str(cycleCount+1)+ “\n”)

print(“Pre-Issue Buffer:”)

issueLen = len(preIssue)

if(issueLen == 0):

print(“\tEntry 0:\t”)

print(“\tEntry 1:\t”)

print(“\tEntry 2:\t”)

print(“\tEntry 3:\t”)

elif(issueLen==1):

print(“\tEntry 0:\t” + ins[preIssue[0]])

print(“\tEntry 1:\t”)

print(“\tEntry 2:\t”)

print(“\tEntry 3:\t”)

elif(issueLen==2):

print(“\tEntry 0:\t” + ins[preIssue[0]])

print(“\tEntry 1:\t” + ins[preIssue[1]])

print(“\tEntry 2:\t”)

print(“\tEntry 3:\t”)

elif(issueLen==3):

print(“\tEntry 0:\t”+ ins[preIssue[0]])

print(“\tEntry 1:\t”+ ins[preIssue[1]])

print(“\tEntry 2:\t”+ ins[preIssue[2]])

print(“\tEntry 3:\t”)

elif(issueLen==4):

print(“\tEntry 0:\t”+ ins[preIssue[0]])

print(“\tEntry 1:\t”+ ins[preIssue[1]])

print(“\tEntry 2:\t”+ ins[preIssue[2]])

print(“\tEntry 3:\t”+ ins[preIssue[3]])

print(“Pre-ALU Queue:”)

aluLen=len(preAlu)

if(aluLen==0):

print(“\tEntry 0:\t”)

print(“\tEntry 1:\t”)

elif(aluLen==1):

print(“\tEntry 0:\t” + ins[preAlu[0]])

print(“\tEntry 1:\t”)

elif(aluLen==2):

print(“\tEntry 0:\t”+ ins[preAlu[0]])

print(“\tEntry 1:\t”+ ins[preAlu[1]])

print(“Post-ALU Queue:”)

aluLen = len(postAlu)

if (aluLen == 0):

print(“\tEntry 0:\t”)

elif (aluLen == 1):

print(“\tEntry 0:\t” + ins[postAlu[0]])

print(“Pre-MEM Queue:”)

aluLen = len(preMem)

if (aluLen == 0):

print(“\tEntry 0:\t”)

print(“\tEntry 1:\t”)

elif (aluLen == 1):

print(“\tEntry 0:\t” + ins[preMem[0]])

print(“\tEntry 1:\t”)

elif (aluLen == 2):

print(“\tEntry 0:\t” + ins[preMem[0]])

print(“\tEntry 1:\t” + ins[preMem[1]])

print(“Post-MEM Queue:”)

aluLen = len(postMem)

if (aluLen == 0):

print(“\tEntry 0:\t”)

elif (aluLen == 1):

print(“\tEntry 0:\t” + ins[postMem[0]])

print(“”)

print(

“r00:” + “\t” + register[0] + “\t” + register[1] + “\t” + register[2] + “\t” + register[3] + “\t” + register[

4] + “\t” + register[5] + “\t” + register[6] + “\t” + register[7] + “\n”)

print(

“r08:” + “\t” + register[8] + “\t” + register[9] + “\t” + register[10] + “\t” + register[11] + “\t” + register[

12] + “\t” + register[13] + “\t” + register[14] + “\t” + register[15] + “\n”)

print(

“r16:” + “\t” + register[16] + “\t” + register[17] + “\t” + register[18] + “\t” + register[19] + “\t” +

print(

“r24:” + “\t” + register[24] + “\t” + register[25] + “\t” + register[26] + “\t” + register[27] + “\t” +

print(“\ndata:\n”)

mem_len = len(addr) – iNum

mem_row_count = mem_len / 8

mem_col_count = (len(addr) – iNum) % 8

count = iNum

for l1 in range(mem_row_count):

if (l1 == (mem_row_count – 1) and mem_col_count > 0):

print(addr[count] + “:” + “\t”)

for l2 in range(mem_col_count):

print(ins[count] + “\t”)

count += 1

print(“\n”)

else:

print(

addr[count] + “:” + “\t” + ins[count] + “\t” + ins[count + 1] + “\t” + ins[count + 2] + “\t” + ins[

count + 3] + “\t” + ins[count + 4] + “\t” + ins[count + 5] + “\t” + ins[count + 6] + “\t” + ins[

count + 7] + “\n”)

count += 8

print(“\n”)

#———————————————MAIN———————————————

def main():

let = len(inst)

for l in range(let):

if (l < len(inst)):

if (inst[l].strip() == “”):

del inst[l]

for l in range(len(inst)):

op.append(“”)

rs.append(“”)

rt.append(“”)

rd.append(“”)

shamt.append(“”)

func.append(“”)

imm.append(“”)

addr.append(“”)

ins.append(“”)

count = 0

for l in range(len(inst)):

ln = inst[l].strip()

if (ln != “”):

checkD.append(ln[0:1])

addr[l] = str(PC + (count * 4))

count = count + 1

else:

checkD.append(“”)

for l in range(len(checkD)):

# ln = inst[l]

if (checkD[l] == “1”):

op[l] = inst[l][1:6]

ins[l] = “”

elif (checkD[l] == “0”):

ins[l] = “Invalid Instruction”

for l in range(len(op) + 1):

if (func[l – 1] == ‘001101’):

iNum = l

break

if (op[l] == “00000” or op[l] == “11100”):

reg(l)

elif (op[l] == “00010”):

j(l)

elif (op[l] == “00011” or op[l] == “00001” or op[l] == “00100” or op[l] == “01011” or op[l] == “01000”):

im(l)

elif (op[l] == “11111”):

ins[l] = “Invalid Instruction”

for l in range(iNum, len(op)):

# print(checkD[l])

if (int(checkD[l]) == 1):

a = int(inst[l], 2) – (1 << 32)

ins[l] = str(a)

elif (int(checkD[l]) == 0):

ins[l] = str(int(inst[l], 2))

for l in range(len(op)):

if (l < iNum):

printThis(l)

else:

printThat(l)

# for l in range(len(op)):

# print(ins[l])

for l in range(32):

regReady.append(True)

cycleCount = 0

#while(not(keepFetching==False and len(preIssue)==0 and len(preMem)==0 and len(preAlu)==0 and len(postMem)==0 and len(postAlu)==0)):

while(cycleCount<10):

WB()

ALU()

MEM()

issue()

iFetch()

printPipeline(cycleCount)

cycleCount += 1

main()

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