Code :
module abc(si,clock,reset,do
);
input clock;
input reset;
input si;
output reg do;
parameter Zero=3’b000,
x1=3’b001,
x2=3’b011,
x3=3’b010,
x4=3’b110;
x5=3’b111;
reg [2:0] cs, ns;
always @(posedge clock, posedge reset)
begin
if(reset==1)
cs <= Zero;
else
cs <= ns;
end
always @(current_state,si)
begin
case(cs)
Zero:begin
if(si==1)
ns <= x1;
else
ns<= Zero;
end
One:begin
if(si==0)
ns<= x2;
else
ns<= x1;
end
OneZero:begin
if(si==0)
ns<= Zero;
else
ns<= x3;
end
x3:begin
if(si==0)
ns<= x2;
else
ns<= x4;
end
x5:begin
if(si==0)
ns<= x2;
else
ns<= x5;
end
default:ns<= Zero;
endcase
end
always @(current_state)
begin
case(current_state)
Zero: do <= 0;
X1: do <= 0;
X2: do <= 0;
X3: do <= 0;
X4: do <= 1;
default: do <= 0;
endcase
end
endmodule
