ELECTRICAL ENGINEERING

QUESTION

University of South Australia            School of Electrical and Information Engineering
EEET 2043 Analogue and Digital Electronic Fundamentals  2012sp2
Practical 3: FET circuits
1. Aim
The aim of this practical is to investigate two applications of FET devices, their use as an amplifier
and their use as a switch. The STP36NF06 NMOSFET is used in the hardware part of this practical
session. This is a 60V, 30A switching device. The datasheets are linked to this prac on learnonline
web page for this subject. Unfortunately Multisim does not have this device, but the IRFZ34N is
very similar.

2. Simulation
Use the first hour of the practical session to simulate all the circuits shown in Figures 1 to 4 on the
following pages. The measurements of voltage and current obtained from these simulations and the
calculated values resulting from them will be used to compare with the corresponding measured
results obtained in part 2 of this practical session.
Screen grabs can be used to record the sketches of the waveforms. Allow space in your prac. book
to insert them.

2.1. FET Amplifier
The FET amplifier shown in figure 1 is required. The amplifier is required to operate from a 15V
supply. For stability, the DC voltage across R2 is required to be about 1V and to obtain a large
voltage swing, an quiescent voltage of 8V is required at the drain of the FET. A 10 mA quiescent
current is required through the FET. Calculate the resistor values R1 and R2 which satisfy these
conditions. (Use the nearest standard resistor values in your circuit).

V1
20 V
1µF
V2
1 Vpk
1kHz
0°
C1
R4

Figure 1. MOS FET amplifier.
R1
R2R3
Vd=11V
Q1
IRFZ34N
Vs=1.5V
Practical 3: FET Circuits Page 1 of 4
University of South Australia            School of Electrical and Information Engineering
EEET 2043 Analogue and Digital Electronic Fundamentals  2012sp2
Use Multisim to plot the VI characteristic of the FET and hence determine the value of V

required to obtain the required quiescent voltage and current. (Insert the VI trace in your lab book).
Use a 100kΩ resistor for R4 and calculate the resistance required for R3 to obtain the desired gate
voltage. Use the nearest standard value in your circuit.
Set the amplitude of the signal source to 0.1mV and compare the measured voltages and current
with the design values.
Observe the drain voltage and increase the signal source amplitude until just after clipping of the
drain voltage occurs. Change R3 to using standard resistor values to check if the maximum output
amplitude can be increased. Using these optimized values, record the input and output waveforms
just before and just after clipping. What is the voltage gain at in input voltage half of that which
causes clipping. Use that input level for all the subsequent tests.
Vary the frequency of the signal source and find the upper and lower bandwidth frequencies
(where the output power is reduced to half, i.e. the voltage gain drops by 1/ √2).

2.2. FET Switch

Figure 2. MOS FET Switch.
Wire up the MOS FET as a switch. Note R3 provides a discharge for any static charge on the gate
and is required in the hardware part of the practical session, to protect the FET. For the simulation
it is required to match the hardware.
For the Drain voltage, determine the rise and fall times (10% to 90% of final values) and the
propagation delay (time to 50% of the final value). Note you may need to change the clock
frequency in order to be able to determine these values.

V1
15 V
V2
1kHz
10 V
R3
100kΩ
R1
4.7kΩ
Q1
IRFZ34N
X1
Probe
Practical 3: FET Circuits Page 2 of 4
gs
University of South Australia            School of Electrical and Information Engineering
EEET 2043 Analogue and Digital Electronic Fundamentals  2012sp2
3. Hardware Design and Measurement
WARNING MOS FET devices have a very high input impedance and can be damaged by
static electricity. Always protect your FET by firstly using a static protected workbench and
secondly to always have a resistor between the gate and source of the FET. (Note some FET’s
include protection diodes to prevent damage). If you wear Nylon or silk underwear, (which
can cause high static voltages) have your prac partner handle the FET’s. When changing R3,
switch off the power supply and first insert the new value of R3, before removing the old
resistor. That minimises the chance of FET damage.
Set the laboratory power supply to the 15V required and set the current limit to 50 mA to minimise
damage due errors. Set the oscilloscope to DC for measuring the Gate, Source and drain voltages.

3.1. FET Amplifier
Using the curve tracer, determine the VI characteristic of your FET. Note how the values obtained
differs from the ones used in Multisim and what changes would you expect that to have on the
amplifier that you simulated using Figure 1.
Using breadboard build the circuits of Figure1, using the resistor values that resulted in the
optimum output voltage swing in the simulation. Measure the gate, drain and source quiescent
voltages and compare that with the simulated values.
If needed change R3 to obtain the maximum output voltage swing. Measure and record the
corresponding relevant (Drain, Source, Gate) voltages.
Comment of your results in comparison with the simulation.
Change the frequency of the signal generator to determine the upper and lower bandwidth
frequencies. (If those frequencies are above or below the frequency range of the signal generator
note that in your prac book).

3.2. FET Switch
Wire up the circuit of Figure 2 and note the behaviour of the FET as a switch and if possible
determine the rise and fall times and the propagation delay. Comment of your results in
comparison with the simulation.

4. Logbook
Your logbook will be assessed based on the following sections.
Preparation (20%), Simulation (20%), Hardware Measurements (40%), Comments and
Practical 3: FET Circuits Page 3 of 4
University of South Australia            School of Electrical and Information Engineering
EEET 2043 Analogue and Digital Electronic Fundamentals  2012sp2
Conclusions (20%).
Marks will be based on the way each section is presented, quality of writing and correctness in
technical content.
5. Equipment List
Lab equipped with computers for using Multisim (1 Hour)
Signal Generator, Digital Oscilloscope.
Breadboard, 1µF capacitor, Various resistors. STP 36NF06 NMOS FET.
Practical 3: FET Circuits Page 4 of 4

SOLUTION

1. According to question,

By kirchoff law,

 

R1=1.1kohm,

 

 

 

 

 

 

 

In loop R3,MOSFET,R2 ,by kirchoff voltage law,

 

 

 

These values are put in circuit.Resistance nearest value is 5.23 ohm.The plot of V-I is given below,

 

 

 

You can check the reports just by clicking ‘reports’ and run the simulation by clicking ‘run’.

 

 

** Design1problem1amplifier **

*

* NI Multisim to SPICE Netlist Export

* Generated by: abhishek

* Wed, Mar 28, 2012 00:46:58

*

 

*## Multisim Instrument XIV1 ##*

XIV1 3 5 7 XXIV1_122936280

 

*## Multisim Component V1 ##*

vV1 4 0 dc 0 ac 1 0

+      distof1 0 0

+      distof2 0 0

+      sin(0 1 1000 0 0 0)

 

*## Multisim Component C1 ##*

cC1 4 3 1e-006

 

*## Multisim Component R4 ##*

rR4 VCC 3 100000 vresR4

.model vresR4 r(  )

 

*## Multisim Component R3 ##*

rR3 0 3 5230 vresR3

.model vresR3 r(  )

 

*## Multisim Component VCC ##*

VCCVCC  VCC 0 dc 20

 

*## Multisim Component R2 ##*

rR2 R2_OPEN_1 R2_OPEN_2 100 vresR2

.model vresR2 r(  )

 

*## Multisim Component R1 ##*

rR1 R1_OPEN_1 7 1100 vresR1

.model vresR1 r(  )

 

*## Multisim Component Q1 ##*

xQ1 7 3 Q1_OPEN_S IRFZ34N__MOS_3TEN__1

 

 

.subckt XXIV1_122936280 1 2 3

v1 3 0 dc 5

v2 1 0 dc 2

r1 2 0 1e-64

.ends

 

.SUBCKT IRFZ34N__MOS_3TEN__1 1 2 3

*      Model Generated by MODPEX     *

*Copyright(c) Symmetry Design Systems*

*         All Rights Reserved        *

*    UNPUBLISHED LICENSED SOFTWARE   *

*   Contains Proprietary Information *

*      Which is The Property of      *

*     SYMMETRY OR ITS LICENSORS      *

*Commercial Use or Resale Restricted *

*   by Symmetry License Agreement    *

* Model generated on Mar  7, 96

* Model format: SPICE3

* Symmetry POWER MOS Model (Version 1.0)

* External Node Designations

* Node 1 -> Drain

* Node 2 -> Gate

* Node 3 -> Source

M1 9 7 8 8 MM L=100u W=100u

* Default values used in MM:

* The voltage-dependent capacitances are

* not included. Other default values are:

*   RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0

.MODEL MM NMOS LEVEL=1 IS=1e-32

+VTO=3.67127 LAMBDA=0 KP=17.6167

+CGSO=6.22832e-06 CGDO=1.97453e-07

RS 8 3 0.0240482

D1 3 1 MD

.MODEL MD D IS=1.01438e-17 RS=0.0101219 N=0.730953 BV=55

+IBV=10 EG=1.2 XTI=4 TT=2.00004e-05

+CJO=5.91562e-10 VJ=1.29493 M=0.482115 FC=0.1

RDS 3 1 1e+06

RD 9 1 0.0001

RG 2 7 2.19574

D2 4 5 MD1

* Default values used in MD1:

*   RS=0 EG=1.11 XTI=3.0 TT=0

*   BV=infinite IBV=1mA

.MODEL MD1 D IS=1e-32 N=50

+CJO=8.11706e-10 VJ=0.50002 M=0.598708 FC=1e-08

D3 0 5 MD2

* Default values used in MD2:

*   EG=1.11 XTI=3.0 TT=0 CJO=0

*   BV=infinite IBV=1mA

.MODEL MD2 D IS=1e-10 N=0.419075 RS=3e-06

RL 5 10 1

FI2 7 9 VFI2 -1

VFI2 4 0 0

EV16 10 0 9 7 1

CAP 11 10 1.15458e-09

FI1 7 9 VFI1 -1

VFI1 11 6 0

RCAP 6 10 1

D4 0 6 MD3

* Default values used in MD3:

*   EG=1.11 XTI=3.0 TT=0 CJO=0

*   RS=0 BV=infinite IBV=1mA

.MODEL MD3 D IS=1e-10 N=0.419075

.ENDS

 

 

 

 

 

 

 

 

 

2.Switch— Check the “Reports” to get reports.You can run the simulation by checking ‘run’.

 

 

** Design2switch-breadboard **

*

* NI Multisim to SPICE Netlist Export

* Generated by: abhishek

* Wed, Mar 28, 2012 07:43:18

*

 

*## Multisim Component V1 ##*

vV1 2 0

+   pulse( 0 10 0 1e-9 1e-9

+   0.0005

+   0.001)

 

*## Multisim Component X1 ##*

* !!!BEGIN-INTERACT

*  : v_level            ++++f2 ;

*  0.0       VARIABLE   r1Volt

*  0.0       VARIABLE   r1Cur

*

*  :UPDATE_SETTINGS

*       0 7 0 SET_SUBCOMP_PRP

*       0 8 0 SET_SUBCOMP_PRP

*       0 9 0 SET_SUBCOMP_PRP

*       0 10 0 SET_SUBCOMP_PRP

*       0 11 0 SET_SUBCOMP_PRP

*       0 12 0 SET_SUBCOMP_PRP

*       0 13 0 SET_SUBCOMP_PRP

*       0.0 ==>_*r1Volt

*       0.0 ==>_*r1Cur

*  ;

*

*  :OUT_DATA

*   GET_INSTANCE Resistor ::R r1 i  ==>_*r1Cur

*   1.0e12 *r1Cur f.*  ==>_*r1Volt

*   v_level *r1Volt  f.<=   if

*       1 7 0 SET_SUBCOMP_PRP

*       1 8 0 SET_SUBCOMP_PRP

*       1 9 0 SET_SUBCOMP_PRP

*       1 10 0 SET_SUBCOMP_PRP

*       1 11 0 SET_SUBCOMP_PRP

*       1 12 0 SET_SUBCOMP_PRP

*       1 13 0 SET_SUBCOMP_PRP

*   else

*       0 7 0 SET_SUBCOMP_PRP

*       0 8 0 SET_SUBCOMP_PRP

*       0 9 0 SET_SUBCOMP_PRP

*       0 10 0 SET_SUBCOMP_PRP

*       0 11 0 SET_SUBCOMP_PRP

*       0 12 0 SET_SUBCOMP_PRP

*       0 13 0 SET_SUBCOMP_PRP

*   endif

*  ;

*

*  :BEGIN_PLOT

*     UPDATE_SETTINGS

*  ;

* !!!END-INTERACT

xX1 1 ProbeX1

.subckt ProbeX1 1

R1 1 0 1e12

.ends

 

*## Multisim Component R2 ##*

rR2 0 2 100000 vresR2

.model vresR2 r(  )

 

*## Multisim Component Q1 ##*

xQ1 1 2 0 IRFZ34N__MOS_3TEN__1

 

*## Multisim Component R1 ##*

rR1 1 VCC 4700 vresR1

.model vresR1 r(  )

 

*## Multisim Component VCC ##*

VCCVCC  VCC 0 dc 15

 

 

.SUBCKT IRFZ34N__MOS_3TEN__1 1 2 3

*      Model Generated by MODPEX     *

*Copyright(c) Symmetry Design Systems*

*         All Rights Reserved        *

*    UNPUBLISHED LICENSED SOFTWARE   *

*   Contains Proprietary Information *

*      Which is The Property of      *

*     SYMMETRY OR ITS LICENSORS      *

*Commercial Use or Resale Restricted *

*   by Symmetry License Agreement    *

* Model generated on Mar  7, 96

* Model format: SPICE3

* Symmetry POWER MOS Model (Version 1.0)

* External Node Designations

* Node 1 -> Drain

* Node 2 -> Gate

* Node 3 -> Source

M1 9 7 8 8 MM L=100u W=100u

* Default values used in MM:

* The voltage-dependent capacitances are

* not included. Other default values are:

*   RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0

.MODEL MM NMOS LEVEL=1 IS=1e-32

+VTO=3.67127 LAMBDA=0 KP=17.6167

+CGSO=6.22832e-06 CGDO=1.97453e-07

RS 8 3 0.0240482

D1 3 1 MD

.MODEL MD D IS=1.01438e-17 RS=0.0101219 N=0.730953 BV=55

+IBV=10 EG=1.2 XTI=4 TT=2.00004e-05

+CJO=5.91562e-10 VJ=1.29493 M=0.482115 FC=0.1

RDS 3 1 1e+06

RD 9 1 0.0001

RG 2 7 2.19574

D2 4 5 MD1

* Default values used in MD1:

*   RS=0 EG=1.11 XTI=3.0 TT=0

*   BV=infinite IBV=1mA

.MODEL MD1 D IS=1e-32 N=50

+CJO=8.11706e-10 VJ=0.50002 M=0.598708 FC=1e-08

D3 0 5 MD2

* Default values used in MD2:

*   EG=1.11 XTI=3.0 TT=0 CJO=0

*   BV=infinite IBV=1mA

.MODEL MD2 D IS=1e-10 N=0.419075 RS=3e-06

RL 5 10 1

FI2 7 9 VFI2 -1

VFI2 4 0 0

EV16 10 0 9 7 1

CAP 11 10 1.15458e-09

FI1 7 9 VFI1 -1

VFI1 11 6 0

RCAP 6 10 1

D4 0 6 MD3

* Default values used in MD3:

*   EG=1.11 XTI=3.0 TT=0 CJO=0

*   RS=0 BV=infinite IBV=1mA

.MODEL MD3 D IS=1e-10 N=0.419075

.ENDS

JD20

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