Question:
Discuss about the VGDL for system Verilog source descriptions.
Answer:
Task – 1
Create a system Verilog source descriptions for the ‘ManchTrans’ block
The timing diagram shows the behaviour of the signals associated with the Manchester Encoding block. Thenon-return to zero data steam is to be a pseudo-Random bit sequence. The PRBS containing the bits (2N-1), where N is a parameter that sets the length of the PRBS shift register. The 100MHz main system divided into result in a data bit rate of 10MBits/second. This pulses are achieved by means of an internal signal.in that pulses are high for one clock period every 10 bits/second.
Figure 1 internal diagram of Manchester transmitter
As shown, this circuit is internal block diagram for the divider clock.it consist of I/O ports in the divider clock. This diagram explain the operation of clock divider.
Creating a SV module for the clock divider
The parameters ‘DIVIDER’ and ‘N’ allow the division ratio.’N’ being the length of the register to divide by ‘DIVIDER’.in the output ‘bit_en’from the ‘divclk’ module enables the pseudo-random bit sequence generator to shift out the next random data bit on the signal. The divider circuit system verilog module created by using the vivado simulator. The divider clock pulses include the bit encoder and bit clock. The below figure shows the system verilog module for divider clock.
Figure 2 creating the SV for divider
When creating the system verilog module for divider clock. The waveform shown in the below:
Figure 3 waveform of divider
VHDL code for clock divider
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
useIEEE.numeric_std.ALL;
entityClock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
endClock_Divider;
architecturebhv of Clock_Divider is
signal count: integer:=1;
signaltmp : std_logic := ‘0’;
begin
process(clk,reset)
begin
if(reset=’1′) then
count<=1;
tmp<=’0′;
elsif(clk’event and clk=’1′) then
count<=count+1;
if (count = 25000) then
tmp<= NOT tmp;
count<= 1;
end if;
end if;
clock_out<= tmp;
end process;
endbhv;
To elaborating the design of divider clock circuit shown in the below format:
It indicates the ports of the divider clock. It includes reset, clock, bit_en, bit_clk in the given circuit design.
Figure 4elobrated execution circuit for divider
Clock divider is also called as Frequency divider. This divider clock is used to divide the frequency of the input clock and also it provides the output clock. Clock divider code of the VHDL consist of two inputs known as Clock and Reset input and this input values are divided using divider clock. Then by this division, the output clock is obtained. The divider clock has the clock source called CLK_PB4, if the process runs in a time then there occurs a change in the input clock value (The Muddy Engineer, 2017). The important factor that is determined in the divider clock is the scaling factor. The formula for determining the scaling factor is represented below.
Creating a SV module for the pseudo-random bit sequence generator
The pcount signal keeps track of the number of bits output during each burst of pseudo-random bits. The both ‘prbs’ and ‘pcount’ outputs are triggered by the input ‘bit_en’ and the corresponding system clock edge. The ‘prbsgen’ module are operate and verify by behavioural simulation using the vivado simulator.Pseudo Random Binary Sequence Generator (PRBS) is an important sequence of binary numbers which are arranged randomly. It is called as Pseudo if the value is deterministic and after certain number of n elements, it starts repeating. It is called as Random binary sequence, if the value of one element is independent with another element. This generator is implemented by the use of Linear Feedback Shift Register. This PRBS generator is used to produce the sequence of binary numbers (PRBS: Pseudo Random Binary Sequence, 2017). The following vhdl code used to create the waveform for pseudo random binary sequence.
Code for prbsgen
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prbsgen is
port ( pclock : in STD_LOGIC;
preset : IN std_logic := ‘0’;
prbsout : out STD_LOGIC);
end prbsgen;
architectureBehavioral of prbsgen is
COMPONENT dff is
PORT(
dclock : IN std_logic;
dreset : IN std_logic;
din : IN std_logic ;
dout : OUT std_logic
);
END COMPONENT;
signaldintern : std_logic_vector (4 downto 1);
signal feedback : std_logic := ‘0’;
begin
instdff :dff port map (pclock , preset , feedback , dintern(1));
genreg : for i in 2 to 4 generate
begin
instdff :dff port map (pclock , preset , dintern(i-1) , dintern(i));
end generate genreg;
main : process(pclock)
begin
ifpclock’event and pclock = ‘1’ then
ifpreset = ‘0’ then
ifdintern /= “0” then
feedback<= dintern(1) xordintern(3);
else
feedback<= ‘1’;
end if;
end if;
end if;
end process main;
prbsout<= dintern(4) ;
endBehavioral;
By using this system verilog code the below format shown in the project manager window.
Figure 5 create SV for prbsgen
The prbsgen system verilog source module create the below waveform for the random sequence.
Figure 6 waveform for prbsgen
The vhdl library code for prbsgen module shown in below format:
Figure 7 VHDL program for prbsgen
Using this vhdl code, the waveform shown in the window.
Figure 8 execution of vhdl
Creating a SV module for the divider error
The module ‘Div_Error the input error pulses are turn on in ‘Error_on’ module. If the logic output error is 0 the output is at logic-0 and the ‘Error_on’ is at logic-1the error pulses are enabled. The 3-bit input named ‘ErrRate’controls the interval between error rates, as per the following data:
All the sequential elements are reset asynchronously by ‘rst’ and clocked on the positive-edge of the ‘clock’. The logic-0 for Error_on the module code divider error shown in below:
Creating the system verilog code in project manager window, the below waveform shown in the behavioural simulation.
When the ErrRate will be logic-1, the Error_on the module code will be enabled. The following waveform indicates the module code and waveform for the divider error.
Creating a SV for the ‘ManchTrans’ block
The module header include the parameters to set the length and feed =back tap position of the PRBSG. The simulation process includes the following values:
Length N=4, feedback taps and Tap Mask=4’b1100. In manchTrans block includes the divider clock, prbsgen, divider error. The following figure indicates the sv for manchtrans block.
Figure 10 creating SV for ManchTrans
The below waveform indicates the behavioural function for the manchtrans block.
Task – 2
Behavioural Simulation of the ‘ManchTrans’ block
Add the source file as a ‘simulation source’ to the design files. Ensure all of the System Verilog design source files you have created in task 1 are also added to the project as design files. Behavioural simulation is the process of employing the abstraction in higher level for modelling the design. It is performed using the VHDL description. This simulation runs faster than other simulation methods. The simulation process takes place in the Manch Trans Block using the encoding and decoding techniques of the Manchester. Manch Tran’s coding method is a type of digital coding method which arranges the binary bits of data in a predefined sequence. If the binary bit of “0” is send in the simulator, the half cycle consists of less voltage and the next cycle is transmitted with high voltage. The encoding and decoding techniques of the Manch Tran block is attained by using the VHDL code (SURESH, 2013).
Create a new simulation source file named ‘Test_ManchTrans.sv’ using the procedure described below:
- Click on the ‘Add Sources’ tool button in the Project Manager group.
- Select ‘Add or Create Simulation Sources’ from the ‘Add Sources’ window.
- Click ‘OK’, then ‘Finish’ then ‘OK’ again to skip the ‘Define Module’ step.
- Test-module source file will be added to the ‘Simulation Sources’ group. Open this file and copy/paste the test-module source.
- Run a behavioural simulation of the design and capture the waveform results, including all relevant signals.The initial simulation sets the error control inputs, ‘Error_on’ and ‘ErrRate’ to zero.
After the synthesis and implementation of the manchtrans block the below waveform will appear in the behavioural simulation window. The value for Error_on is 1 and the ErrRate will be 5 is modified in the project manager window. Now the waveform became shown this below format:
Task – 3
Different types of simulation process
Vivado is a kind of software that can be used for the simulation process. This simulator is rich in its features and it is capable in supporting mixed languages. It can support description languages like Verilog, System Verilog and the VHDL language. In this project, VHDL language is used for coding. The vivado simulator does not require any cost for maintaining it. This simulator does not have a fixed size for its design or does not have any limitations. It can permit many number of unlimited instances in a mixed language. It is supported in windows as well as in Linux OS. This simulator is capable of allowing types of simulations like behavioural simulation, functional simulation and the timing simulation (Xilinx.com, 2017).
Logical Simulation
Logic simulation is the process of permitting the designer to perform a type of virtual test in the digital circuit before getting initiated with any type of hardware. The test is performed on the digital circuit which is very complex in nature. If the design is found to be suitable then the logical simulation, makes the process easy for optimizing, debugging and modifying the digital circuit. The vivado integrated design environment launches the logic simulation using the simulation commands and the files that are required for simulation. The target and the simulator language is being selected in the vivado simulator. Logic simulation is also called as true value simulation. The main objective of the logic simulation is calculating the logic values in an accurate way which is implied at the line. The timing of the transition values of the logic circuit is calculated. Each logic block of the synchronous sequential circuit is simulated. This simulation is known as the cycle based simulation (Vivado Design Suite Tutorial: Logic Simulation, 2017).
Timing Simulation
Timing Simulation is the emulation process that downloads a design to the device. The timing simulation is performed by compiling and synthesizing the design by the use of anyone of the target devices. The first step that is to be carried out for the timing simulation is placing and routing the design of the circuit. At the post simulation stage of the synthesis process, the timing simulation is carried out using the timing numbers which are estimated already. Flow navigator is used for performing the timing simulation process in the vivado simulator. Command line can also be used for performing the timing simulation. Then the net list file has to be generated for performing the timing simulation using vivado. Therefore the process that exercises the models of functions and the timing of a net list by the application of the input stimuli for observing the responses of the timing is known as timing simulation. Once the design is implemented, the simulation settings is selected to mention the type of simulation. The target simulator is selected first as the Active HDL simulator. Then the simulation tab is used to specify the kind of simulation. The option called “Run Simulation” is selected and then from the options specified in the Run Simulation, Run Post-Implementation Timing Simulation is selected (Post-Implementation Timing Simulation, 2017).
Functional Simulation
Functional Simulation can be performed after the process of creating the test bench and the code of design on the design of the circuit. This process is called as an iterative process, as it needs multiple number of simulations which can be used for achieving the functional design of the digital circuit. This process permits the testing process to be done automatically and it is used to decrease the number of changes that are carried out in the regression process of the functional design of the circuit. This kind of simulation requires a proper infrastructure. As the timing simulation, the functional simulation is performed using the same steps in the vivado simulator. The flow navigator option is selected from the simulation settings of the vivado simulator. In the simulator settings, the option called Run simulation is selected. In the Run Simulation option, there may occur many types of simulation. From the listed options, Run Post Implementation Functional Simulation is carried out. Command line can also be used for performing the functional simulation process. The functional simulation is performed using the command line by generating the netlist of the functional simulation.
Behavioural Simulation
Behavioural Simulation is performed after the process of synthesis along with the behavioural model process. It can be performed by performing the following steps
- Test Benches using HDL
- Test bench using waveform files
- Behavioural Simulation
This behavioural simulation is performed using the verify syntax of the code. The simulation can be performed using Vivado IDE and also using the command line. The waveform window is the window which represents the 4 input values and one output for the simulated design. This simulation can be used for verifying the syntax and the function of the design of the circuit without specifying the information about the time (Gist, Hopper and Daniels, 2015).
- Behavioural simulation
- Post –synthesis functional
- Post – synthesis timing simulation
- Post – implementation functional simulation
- Post – implementation timing simulation
Post – synthesis functional
The vivado using the post –synthesis running function, the error will be occur.The test bench files is not properly compiled. The error may be arrive the vivado generated usually due to missing the project file you check project file Project file is automatically generated the missing file.You can using the given following below methods. Create project file in custom and simulation run from command line Source window update the mode in check hierarchy moreit is set to “compile order and automatic update”. The properties must check in the test bench file and simulation includes Used In property.
Synthesis and Implementation of the ‘ManchTrans’ block
Figure 11 synthesis for ManchTrans
The synthesis process completed successfully, the below synthesized desisn shown in the window.
Figure 12 synthesised design for ManchTrans
Task – 4
Post-Implementation Timing Simulation of ‘ManchTrans’ block
Close the ‘Synthesized Design’ window by clicking on the ‘X’ at the top-right-hand corner of the window (not the one in the TRHC of the main Vivado window, as this will close the entire Program). Click on, ‘Implementation → Run Implementation’ in the Flow Navigator, to invoke the implementation process. Once implementation has completed successfully it will be possible to run a Post-Implementation Timing Simulation. Run the simulation and copy/paste clear images of the simulation results into your assignment report, showing a variety of views (full and zoomed-in) with, and without, errors turned on. Include only the top-level test-module signals. Compare the post-implementation timing simulation results with those obtained in task 2 and write down comments on any differences.
Code for test_ManchTrans.sv
module test_ManchTrans( );
//inputs
logic clock, rst, clr_pcount;
logic Error_on;
logic [2:0] ErrRate;
//outputs
logicman_tx, man_bit_clk, nrz, transmit_bit_enable;
logic [3:0] Pcount;
//100MHZ clock
initial begin
clock = 1’b0;
forever
#5 clock = ~clock;
end
initial begin
rst = 1’b1;
clr_pcount = 1’b0;
Error_on = 1’b0;
ErrRate = 0;
repeat (5) @(negedge clock);
rst = 1’b0;
repeat (205) @(negedge clock);
clr_pcount = 1’b1;
repeat (1) @(negedge clock);
clr_pcount = 1’b0;
repeat (200) @(negedge clock);
$stop;
end
endmodule : test_ManchTrans
Figure 13 create SV for test_ManchTrans
Figure 14 elaborated circuit for ManchTrans
Task – 5
Create SV source descriptions for the Manchester Receiver (ManchRecv) block
The digital data stream coming out of the receiver side of the communication system enters a shift register at the ‘man_rx’ input. The main system 100MHz clock samples and shifts the incoming bits into the shift register most significant bit. The contents of the shift register are shifted to the right on each positive-edge, the resulting parallel 10-bit value is present on the ‘data’ output port. This process is illustrated by the diagram below:
Figure 15 create SV for test_ManchTrans_Recv
Create a SV source description for the ‘rx_shift_register’ sub-block
- The length of the shift register is set by a parameter ‘N’ having a default value of 10
- The shift register is asynchronously cleared to all zeros when ‘rst’ is taken to logic-1.
Figure 16 create SV for rx_shift_register
The remaining part of the Manchester receiver block diagram of Finite State Machine (FSM), the purpose of which is to detect the sequence of ‘sync’ pulses coming from the ‘syncdet’ block and use these to synchronise to the ‘man_rx’ data stream and extract the following three signals:
- RNRZ – Recovered Non-Return-to-Zero data bits
- RBC – Recovered Bit Clock (10MHz, synchronised to RNRZ data)
- RBE – Recovered Bit Enable, this is a single clock pulse length pulse occurring at the mid-point of each RNRZ data bit.
Creating the finite state machine system verilog source code in vivado simulator the below waveform shown in the behavioural simulation window.
Task – 6
Simulation of the Manchester Transmitter and Receiver modules
Open the SV source file for the ‘test_ManchTrans’ module and save itunder the new filename ‘test_ManchTrans_Recv.sv’. Modify the ‘test_ManchTrans_Recv.sv’ test-module by adding an instance of the Manchesterreceiver module developed in the previous task along with an instance of the ‘TransDelay’module,also provided in the appendix, setting the transmission delay to be 33.0e-9 seconds. The new test-module, make use of signal names that allow automated connection to be used wherever possible.
Add the new simulation module ‘test_ManchTrans_Recv.sv’ to the project as a simulation source and set it to be the top-level module in the ‘Simulation Sources’ hierarchy tree in the sources window. By creating the test_manch_trans_Recv SV module in the simulator, the below format shown in the project manager window.
The elaborated design for test_manch_trans receiver shown in below figure:
The waveform starts from 0 to 600ns the below figure shown in the window
The waveform starts from 0ns to 900ns the below figure shown in the window.
Figure 17 waveform for test_ManchTrans_Recv
Task -7
Explanation of the Digital Delay block
Digital delay development based on the digital signal processing .the digital delay is firstPedal was Boss DD-2. This delay evolved reverb in digital multi-effects. Initially this available Expensive rack-mounted unit. Digital multi-effect units is pure delay as reverb and Audio timescale-pitch modification effect. The function of digital delay system is sampling the analog-to- digital converter, and input signal. After that the signal passes the series of digital signal processor. Buffer is used to this record and storage. Store audio is based on the user set by the parameter play back. The output of delayed (wet) mixed with unmodified (dry) after the signal or before. This sent to a digital-to- analog.
Delay parameter
The filter is using to shape of the output of the delay signal. The input of delayed signal chain to create echo.
- Low cut filter
- High cut filter
Feedback delay
The basic delay effect, is usually some feedback. This function is used to how much of the fed back through the effect and providing the multiple repetition of the processed signal.
Auto reset
Supply voltage range 110-240VAC and display of digital 7-segment.The sensing range of input signal is 85-265VAC /100-265VDC and 20-60VAC/DC Covering of Majority application in inbuilt library 33 functions. The function of program is easy to customize.
Features
Auto reset-no buttons to press
Programmable kill time
Programmable shift on and off pulse time
Two RPM range 3000-9000 RPM and 10,100 to 19900 RPM
Auto shift programmable for each shift.
Specification
- Multiple RAM setting
- 40 Amp rated output shift
- 15 Amp rated output kill
Voltage controller oscillator
It is controlled by the input dc voltage. The oscillation frequency is directly relalted to thevoltage input and it is varies from few hertz to 100 GHZ. If varying DC input, the output
Frequency of the signal produced by adjusted.
Application of VCO
- Using to function generator.
- Phase locked loop
- Communication circuits used frequency synthesizers.
- Digital elevation model
- Digital model is a digital elevation model (DEM).
- It is a 3D representation of a terrains surface. It is create from the terrain elevation data.
Task -8
Create the System Verilog source description for the match counter and complete the‘DelayComp’ block
The operation of the ‘match_count’ module was described earlier. A match occurs when theDelayed version of ‘TBE’ (‘TBED’) coincides with the ‘Received Bit Enable’ (RBE) and, during the same clock-cycle, the value of the delayed version of ‘NRZ’, ‘NRZD’ matches the recovered non-return-to-zero data value, ‘RNRZ’.Add SV statement to the above incomplete source description and save the file under the name ‘match_count.sv’.
The register named ‘q’ stores a 4-digit BCD number, where each group of 4-bits represents a decimal digit. Add the design file to the Vivado project, correcting any syntax errors that may be flagged in the source.
Task -9
Combine the ManchTrans, ManchRecv and DelayComp modules into a test-module andperform behavioural simulations
The three modules developed above are to be combined in a test-module in order to verify correct operation of the ‘DelayComp’ module. Figure 5a shows the structure of the test-module source description ‘test_ManchTrans_Recv_DelayComp.sv’.Open the last test-module you created (test_ManchTrans_Recv.sv) and copy all of the source textinto a new file, saving it under the name ‘test_ManchTrans_Recv_DelayComp.sv’. This will mainly involve adding an instance of the ‘DelayComp’ module and associated signals. At this point the contents of the second initial block can be left unchanged apart from adding statements to initialise any new signals to zero. Add the new test-module to the Vivado project as a simulation source, and set it to be the top-level simulation source.
Figure 18 create SV for test_ManchTrans_Recv_Delaycomp
Select the new test-module and run a behavioural simulation, at this point you may receive error messages if any of the source files contain syntax errors. These must be corrected before re-launching the simulator. Once the simulation has started successfully, go to the ‘Scopes’ panel and click on the instance of the ‘DelayComp’ module. Select the internal signals ‘NRZD’ and ‘TBED’ and add them to the waveform window. Select the signal named ‘m_count’ and change the radix to Hexadecimal. Set the radix for ‘Pcount’and ‘Delay’ to the decimal.
Restart (Run – Restart…) and run (Run – Run All…) to update the waveforms.
s
Task -10
Addition the ‘Sync_control’ block and simulation of the complete BERT system
The synchronisation control block monitors the number of pseudo-random bits that have beenTransmitted (Pcount) and, when this reaches a value set by the module parameter ‘NumPatt’, transfers the 4-digit BCD value of ‘m_count’to the display driver circuit. This results in the display being updated with the number of correctly received bits after every burst of ‘NumPatt’ bits transmitted. Another parameter, ‘SyncThresh’ is compared with ‘m_count’, such that if the match count exceeds the synchronisation threshold, the system is synchronised and the ‘SyncLED’ is illuminated.
The module header for the synchronisation control module
module sync_control_v3 #(parameter P = 10,
SyncThresh = 16’h0000, //must be BCD format
NumPatt = 1000)
(input logic clock, rst,
input logic [P-1:0] Pcount,
input logic [15:0] m_count,
output logic clr_match,
output logic clr_pcount, //change to clr_pcount
output logic InSync,
output logic [15:0] DispMatchCount);
Figure 19 create SV for sync_control
Figure 20 waveform for sync_control
Task -11
Simulation of the complete BERT system
To Create a SystemVerilog source description for the top-level Bit Error Rate Tester system making use of consistent interconnection names to exploit automated connection wherever possible. The version of the top-level design does not require the inclusion of the ‘Display Driver’ block, this will be added prior to implementation. When instantiating the sub-modules within the top-level ‘BERT’ module, set the parameters as follows:
ManchTrans: N = 10, TapMask = 10-bit feedback mask to give maximal length sequence
DelayComp: D = 8
Sync_control: P = 10, SyncThresh = 16’h0055, NumPatt = 101
Task -12
Set the parameters of the ‘SyncControl’ block for implementation, this will involve changing
‘SynchThresh’ and ‘NumPatt’, the latter being 100110. The instance of the display counter, ‘dispcntr’, should be configured to refresh the 4-digit display at a suitable rate.
To change the syncntrl module value for synctresh and numpattn=100110 the below window appear in the project manager task.
The master constraint file, ‘Basys3_Master.xdc’, must be edited and save under the name ‘BERT.xdc’, in order to assign FPGA pins to the top-level input/outputs of the design. The dispmux,dispcunt and BCD2 segments are combine to the BERT system.these system are to execute the fpga pin diagram.these Verilog system are saved under the name in BERT.xdc.
After completing the synthesis and implementation of the BERT.xdc the below format appear in the window.
After completing of synthesis and implementation of the BERT.xdc, the file save under the name in BERT.bit. now to target the file to the hardware manager in the navigator window.
Finally the schematic diagram for the RTL display shown in below format:
References
Gist, M., Hopper, H. and Daniels, D. (2015). Behavioral Simulation: Application and Potential in Management Research. Organizational Research Methods, 1(3), pp.251-295.
Post-Implementation Timing Simulation. (2017). [online] Available at: http://www.eng.auburn.edu/~nelson/courses/elec4200/Lab_Files/Post%20Implementation%20Timing%20Simulation.pdf [Accessed 8 Nov. 2017].
PRBS : Pseudo Random Binary Sequence. (2017). [online] Available at: http://www.cs.huji.ac.il/course/2002/vlsilab/files/prbs/PRBS.pdf [Accessed 8 Nov. 2017].
SURESH, S. (2013). VHDL IMPLEMENTATION OF MANCHESTER ENCODER AND DECODER. International Journal of Electrical, Electronics and Data Communication, ISSN (p): 2320-2084, 1(2).
The Muddy Engineer. (2017). VHDL Clock Divider – The Muddy Engineer. [online] Available at: https://www.muddyengineer.com/vhdl-clock-divider/ [Accessed 8 Nov. 2017].
Vivado Design Suite Tutorial: Logic Simulation. (2017). [online] Available at: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug900-vivado-logic-simulation.pdf [Accessed 8 Nov. 2017].
Xilinx.com. (2017). Functional Simulation. [online] Available at: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_simulation_functional.htm [Accessed 8 Nov. 2017].
Xilinx.com. (2017). Performing Behavioral Simulation. [online] Available at: https://www.xilinx.com/itp/xilinx10/isehelp/pp_p_process_simulate_behavioral_model.htm [Accessed 8 Nov. 2017].
Xilinx.com. (2017). Timing Simulation. [online] Available at: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_simulation_timing.htm [Accessed 8 Nov. 2017].
Xilinx.com. (2017). Vivado Simulator. [online] Available at: https://www.xilinx.com/products/design-tools/vivado/simulator.html [Accessed 8 Nov. 2017].
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## – uncomment the lines corresponding to used pins
## – rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property PACKAGE_PIN W5 [get_ports CLK100M]
set_property IOSTANDARD LVCMOS33 [get_ports CLK100M]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK100M]
## Switches
set_property PACKAGE_PIN V17 [get_ports sw[0]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
set_property PACKAGE_PIN V16 [get_ports sw[1]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
set_property PACKAGE_PIN W16 [get_ports sw[2]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
set_property PACKAGE_PIN W17 [get_ports sw[3]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
set_property PACKAGE_PIN W15 [get_ports sw[4]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
set_property PACKAGE_PIN V15 [get_ports sw[5]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
set_property PACKAGE_PIN W14 [get_ports sw[6]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
set_property PACKAGE_PIN W13 [get_ports sw[7]]
set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
#set_property PACKAGE_PIN U16 [get_ports LED0]
#set_property IOSTANDARD LVCMOS33 [get_ports LED0]
#set_property PACKAGE_PIN E19 [get_ports LED1]
#set_property IOSTANDARD LVCMOS33 [get_ports LED1]
#set_property PACKAGE_PIN U19 [get_ports LED2]
#set_property IOSTANDARD LVCMOS33 [get_ports LED2]
#set_property PACKAGE_PIN V19 [get_ports LED3]
#set_property IOSTANDARD LVCMOS33 [get_ports LED3]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
set_property PACKAGE_PIN W7 [get_ports CA]
set_property IOSTANDARD LVCMOS33 [get_ports CA]
set_property PACKAGE_PIN W6 [get_ports CB]
set_property IOSTANDARD LVCMOS33 [get_ports CB]
set_property PACKAGE_PIN U8 [get_ports CC]
set_property IOSTANDARD LVCMOS33 [get_ports CC]
set_property PACKAGE_PIN V8 [get_ports CD]
set_property IOSTANDARD LVCMOS33 [get_ports CD]
set_property PACKAGE_PIN U5 [get_ports CE]
set_property IOSTANDARD LVCMOS33 [get_ports CE]
set_property PACKAGE_PIN V5 [get_ports CF]
set_property IOSTANDARD LVCMOS33 [get_ports CF]
set_property PACKAGE_PIN U7 [get_ports CG]
set_property IOSTANDARD LVCMOS33 [get_ports CG]
set_property PACKAGE_PIN V7 [get_ports DP]
set_property IOSTANDARD LVCMOS33 [get_ports DP]
set_property PACKAGE_PIN U2 [get_ports AN0]
set_property IOSTANDARD LVCMOS33 [get_ports AN0]
set_property PACKAGE_PIN U4 [get_ports AN1]
set_property IOSTANDARD LVCMOS33 [get_ports AN1]
set_property PACKAGE_PIN V4 [get_ports AN2]
set_property IOSTANDARD LVCMOS33 [get_ports AN2]
set_property PACKAGE_PIN W4 [get_ports AN3]
set_property IOSTANDARD LVCMOS33 [get_ports AN3]
##Buttons
set_property PACKAGE_PIN U18 [get_ports RESET]
set_property IOSTANDARD LVCMOS33 [get_ports RESET]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
set_property PACKAGE_PIN U17 [get_ports ManConv]
set_property IOSTANDARD LVCMOS33 [get_ports ManConv]
##Pmod Header JA
##Sch name = JA1
set_property PACKAGE_PIN J1 [get_ports JA[0]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[0]]
#Sch name = JA2
set_property PACKAGE_PIN L2 [get_ports JA[1]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[1]]
#Sch name = JA3
set_property PACKAGE_PIN J2 [get_ports JA[2]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[2]]
#Sch name = JA4
set_property PACKAGE_PIN G2 [get_ports JA[3]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[3]]
#Sch name = JA7
set_property PACKAGE_PIN H1 [get_ports JA[4]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[4]]
#Sch name = JA8
set_property PACKAGE_PIN K2 [get_ports JA[5]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[5]]
#Sch name = JA9
set_property PACKAGE_PIN H2 [get_ports JA[6]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[6]]
#Sch name = JA10
set_property PACKAGE_PIN G3 [get_ports JA[7]]
set_property IOSTANDARD LVCMOS33 [get_ports JA[7]]
##Pmod Header JB
##Sch name = JB1
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
##Sch name = JB2
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
##Sch name = JB3
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
##Sch name = JB4
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
##Sch name = JB7
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
##Sch name = JB8
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports JC[0]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[0]]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports JC[1]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[1]]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports JC[2]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[2]]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports JC[3]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[3]]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports JC[4]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[4]]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports JC[5]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[5]]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports JC[6]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[6]]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports JC[7]]
# set_property IOSTANDARD LVCMOS33 [get_ports JC[7]]
##Pmod Header JXADC
##Sch name = XA1_P
set_property PACKAGE_PIN J3 [get_ports VAUXP6]
set_property IOSTANDARD LVCMOS33 [get_ports VAUXP6]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
set_property PACKAGE_PIN K3 [get_ports VAUXN6]
set_property IOSTANDARD LVCMOS33 [get_ports VAUXN6]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
#set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
#set_property PULLUP true [get_ports PS2Data]
##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
module bcd2seg #(parameter Active_High = 0)
(input logic [3:0] bcdin,
output logic CA, CB, CC, CD, CE, CF, CG);
logic [6:0] temp;
always_comb
case(bcdin) //active-low codes
4’h0 : temp = 7’b0000001;
4’h1 : temp = 7’b1001111;
4’h2 : temp = 7’b0010010;
4’h3 : temp = 7’b0000110;
4’h4 : temp = 7’b1001100;
4’h5 : temp = 7’b0100100;
4’h6 : temp = 7’b0100000;
4’h7 : temp = 7’b0001111;
4’h8 : temp = 7’b0000000;
4’h9 : temp = 7’b0000100;
4’hA : temp = 7’b0001000;
4’hB : temp = 7’b1100000;
4’hC : temp = 7’b0110001;
4’hD : temp = 7’b1000010;
4’hE : temp = 7’b0110000;
4’hF : temp = 7’b0111000;
endcase
assign {CA, CB, CC, CD, CE, CF, CG} = (Active_High)? ~temp : temp;
endmodule : bcd2seg
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.11.2017 02:30:01
// Design Name:
// Module Name: dig_delay
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 – File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dig_delay #(parameter N = 8)
(input logic clock, rst, Din,
input logic [N-1:0]
Delay,
output logic Dout);
logic
[2**N – 1:0]q;
always_ff @(posedge clock, posedge rst)
begin
if
(rst == 1’b1)
q <= 0;
else
q <= {q[2**N – 2:0], Din};
end
assign Dout = q[Delay];
endmodule : dig_delay
//modified for BASYS3 Board with 100MHz input clock
module dispcntr #(parameter N = 2)
(input logic Clk, Reset,
output logic AN0, AN1, AN2, AN3, //active-low anodes
output logic [1:0] sel);
//divides clock input by 2**N
//used by multiplexed displays
//set N = 2 for simulation and
//N = 22 for implementation (100e6/2**20 = 95Hz)
reg [N-1:0] count;
always_ff @(posedge Clk or posedge Reset)
begin
if (Reset == 1’b1)
count <= 0;
else
count <= count + 1;
end
assign sel = count[N-1:N-2]; //top 2 bits of count
//active low common anodes
assign AN0 = ~(sel == 0);
assign AN1 = ~(sel == 1);
assign AN2 = ~(sel == 2);
assign AN3 = ~(sel == 3);
endmodule : dispcntr
module dispmux (input logic [15:0] datain,
output logic [3:0] bcd_out,
input logic [1:0] sel);
//16-to-4 mux for display
always_comb
case (sel)
0 : bcd_out = datain[3:0];
1 : bcd_out = datain[7:4];
2 : bcd_out = datain[11:8];
3 : bcd_out = datain[15:12];
endcase
endmodule : dispmux
module XADC_Controller(input logic Clk, Reset, trigger, //’trigger’ starts conversion
input logic ADC_Busy, ADC_EOC, Data_Rdy,
output logic Data_En, ADC_SC,
input logic [15:0] ADC_Data_in,
output logic [15:0] ADC_Data_out,
output logic [6:0] ADC_Address);
typedef enum logic [3:0] {RES = 0, DADDR, WT_TRIG, SC_HI, SC_LO,
WT_EOC, DEN_HI, DEN_LO, WT_DRDY, GET_DATA} state_t;
var state_t pstate, nstate;
//state register
always_ff @(posedge Clk or posedge Reset)
if (Reset == 1’b1)
pstate <= RES;
else
pstate <= nstate;
//next state
always_comb
unique case (pstate)
RES : nstate = DADDR;
DADDR : nstate = WT_TRIG;
WT_TRIG : nstate = (trigger == 1’b1)? SC_HI : WT_TRIG;
SC_HI : nstate = SC_LO;
SC_LO : nstate = WT_EOC;
WT_EOC : nstate = (ADC_EOC == 1’b1)? DEN_HI : WT_EOC;
DEN_HI : nstate = DEN_LO;
DEN_LO : nstate = WT_DRDY;
WT_DRDY : nstate = (Data_Rdy == 1’b1)? GET_DATA : WT_DRDY;
GET_DATA : nstate = WT_TRIG;
default : nstate = RES;
endcase
//Register Transfer Operations
always_ff @(posedge Clk) begin : RTL
unique case (pstate)
RES : begin
Data_En <= 0;
ADC_SC <= 0;
ADC_Data_out <= ‘0;
ADC_Address <= ‘0;
end
DADDR : ADC_Address <= 7’h16;
SC_HI : ADC_SC <= 1;
WT_EOC : ADC_SC <= 0;
DEN_HI : Data_En <= 1;
DEN_LO : Data_En <= 0;
GET_DATA : ADC_Data_out <= ADC_Data_in;
default : ; //do nothing 2/9/16
endcase
end : RTL
endmodule : XADC_Controller
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 29.01.2016 17:13:29
// Top-level design file for XADC with RTL Controller and 4 digit hex display
//modified September 2016 to include 8 switches as input driving 8 digital outputs to R-2R DAC for testing.
//////////////////////////////////////////////////////////////////////////////////
module XADC_RTL_Display(
input logic RESET,
input logic CLK100M,
input logic VAUXP6, //analogue input
input logic VAUXN6,
output logic CA, //display signals
output logic CB,
output logic CC,
output logic CD,
output logic CE,
output logic CF,
output logic CG,
output logic DP,
output logic AN0,
output logic AN1,
output logic AN2,
output logic AN3,
input logic [7:0] sw, //input sliding switches
output logic [7:0] JA, //output bits to R-2R DAC
input logic ManConv //push-button manual convert command (BTND)
);
//XADC input signals
logic DEN, SC;
//XADC output signals
logic DRDY, BUSY, EOC;
//XADC data output
logic [15:0] XADC_DO;
//XADC address input (selects ADC result register)
logic [6:0] DADDR;
//display signals
logic [15:0] DISP_DATA;
logic [3:0] bcdin;
logic [1:0] sel;
logic Clk, Reset, trigger;
logic q0, q1;
assign Clk = CLK100M;
assign Reset = RESET;
//connect switches to DAC
assign JA = sw;
//instantiation of XADC
xadc_wiz_0
ADC1(.convst_in(SC),
.daddr_in(DADDR),
.dclk_in(Clk),
.den_in(DEN),
.di_in(),
.dwe_in(1’b0),
.reset_in(Reset),
.vauxp6(VAUXP6),
.vauxn6(VAUXN6),
.busy_out(BUSY),
.channel_out(),
.do_out(XADC_DO),
.drdy_out(DRDY),
.eoc_out(EOC),
.eos_out(),
.alarm_out(),
.vp_in(),
.vn_in());
XADC_Controller CON1(.ADC_Busy(BUSY), .ADC_EOC(EOC), .Data_Rdy(DRDY),
.Data_En(DEN), .ADC_SC(SC),
.ADC_Data_in(XADC_DO),
.ADC_Data_out(DISP_DATA),
.ADC_Address(DADDR), .*);
//for simulation set NUMCLKS to 200 and n to 8
//for implementation use .NUMCLKS(1000000), .n(20)
Timer #(.NUMCLKS(200), .n(8)) //100Hz pulse
TMR1(.Pulse(trigger), .*);
//manual convert start button (use as alternative to above Timer)
//always_ff @(posedge Clk) begin : pushbutton
// q0 <= ManConv;
// q1 <= q0;
//end : pushbutton
//assign trigger = q0 & ~q1;
//end of manual start conversion button
//display logic
assign DP = 1’b1; //turn off decimal points
bcd2seg BCD2SEG1(.*);
dispmux DMUX1(.datain(DISP_DATA), .bcd_out(bcdin), .*);
//set N = 2 for simulation and 22 for implementation
dispcntr #(.N(2)) DCNTR1(.*);
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.11.2017 02:14:09
// Design Name:
// Module Name: sync contrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 – File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sync_control_v3 #(parameter P = 10,
SyncThresh = 16’h0000, //must be BCD format
NumPatt = 1000)
(input logic clock, rst,
input logic [P-1:0] Pcount,
input logic [15:0] m_count,
output logic clr_match,
output logic clr_pcount, //change to clr_pcount
output logic InSync,
output logic [15:0] DispMatchCount);
endmodule
